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MITSUBISHI DIGITAL ASSP MITSUBISHI DIGITAL ASSP
M66010FP/GP M66010FP/GP
24-BIT I/O EXPANDER 24-BIT I/O EXPANDER
DESCRIPTION M66010 Semiconductor Integrated Circuit inputs 24-bit data in series and outputs it in parallel and vice versa, using shift register function. Equipped with 2 independent shift registers, one for serial-toparallel, the other for parallel-to-serial, this IC is able to read serial input data into a shift register while converting data from parallel to serial. Parallel input/output pins are set to input or output according to the bit. The M66010 is useful in a wide range of applications, such as MCU (micro controller unit) input/output port extension and serial bus system data communication. FEATURES * Two-way serial data communication with MCU * Serial data intake possible during parallel-to-serial conversion * Parallel input/output switchable according to the bit * Low power dissipation: 100W maximum per package (VCC =5V, Ta = 25C, quiescent) * Schmidt input (DI, CLK, S, CS) * Open drain output (DO, D1 thru D24) * Parallel data input and output (D1 thru D24) * Wide operating supply voltage range (VCC = 2V ~ 6V) APPLICATION MCU-related serial-parallel data conversion, serial bus control by MCU, etc. FUNCTION The M66010 is produced by using the silicon gate CMOS (complementary metal-oxide semiconductor) technology. It is distinguished for low power dissipation and high noise resistance. Because two independent shift registers are built in, one for serial-to-parallel, the other for parallel-to-serial, this IC is able to read serial input data into a shift register while converting parallel data into serial data. One cycle of latching 24-bit parallel data and outputing it in series while taking in serial data from MCU is initiated by CS's shift from "H" to "L". At CS fall edges, 24-bit parallel data is latched, and output in series from pin DO synchronously with shift clock fall edges. At shift clock rise edges, serial data is taken in from MCU via pin DI. The data is read into shift register. The 25th and following shift clock pulses are ignored and read-in operation is masked. The pin D0 status shifts to high-impedance. As CS is then shifted from "L" to "H", 24-bit serial data taken in via pin DI is output in parallel to pins D1 thru D24. Because parallel output pins are the n-channel open drain output type, write data "H" for pins which should be set to input.
PIN CONFIGURATION (TOP VIEW)
SERIAL DATA OUTPUT SERIAL DATA INPUT CLOCK INPUT CHIP SELECT INPUT SET INPUT
PARALLEL DATA I/O
D0 D1 CLK CS VCC S GND D24 D23 D22 D21 D20 D19 D18 D17 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DO DI CLK CS S D24 D23 D22 D21 D20 D19 D18 D17
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
D1 D2 D3 D4 D5 D6 D7 PARALLEL D8 DATA D9 I/O D10 D11 D12 D13 D14 D15 D16
Outline 32P2W-A 32P2U-B
OPERATION (1) When power is turned on, the status of pins D0 and D1 thru D24 is unstable. Their status turns high-impedance when S is shifted to "L". (2) At CS fall edges, the status of pins D1 thru D24 is loaded on shift register 1. (3) At CLK fall edges, 24-bit data loaded as described above is output in series from pin D0. (4) At CLK rise edges, 24-bit serial data is taken in from pin DI and written on shift register 2. (5) The 25th and following CLK pulses are ignored, and serial data write is discontinued. Pin D0 status turns high-impedance. (6) At CS rise edges, data written as described in (4) is output to pins D1 thru D24. (7) Shift register 1 loads data added from outside as well as AND tie data which has the same contents as data latched by serial output latch. (8) If the CS rises before CLK reaches the 24th bit, parallel output latch latches data which has been written on shift register, and output it to pins D1 thru D24. (9) Pins D1 thru D24 are switched between input and output according to serial data input to pin DI. Pins for which "H" is written are set to input.
1
MITSUBISHI DIGITAL ASSP
M66010FP/GP
24-BIT I/O EXPANDER
BLOCK DIAGRAM
VCC 5 Shift register 1 DO D3 D2 D1 1 DO SERIAL DATA OUTPUT
Control circuit
CLOCK INPUT CLK
3
D24 D23 D22
32 D1 31 D2 30 D3 Q24 Q23 Q22 Q3 Q2 Q1 Parallel output latch D24 D23 D22 D3 D2 D1 Q24 Q23 Q22 Q3 Q2 Q1 10 D22 9 D23 8 D24 7 16 GND GND PARALLEL DATA I/O
SET INPUT CHIP SELECT INPUT
S
6
CS
4
Shift register 2 SERIAL DATA INPUT DI DI 2
VCC
VCC
VCC
CLK S CS DI
DO
D1~D24
Input type
Output type
OPERATION TIMING CHART
S (1) (2) CS (5) CLK 1 2 (4) DI DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO23 DO24 High impedance DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI23 DI24 (6) D1 DI1 D01 3 4 5 6 7 8 9 10 23 24 25 H L
(3) DO DI1
D2
DI2
D02
D24
DI24 One cycle
D024
2
MITSUBISHI DIGITAL ASSP
M66010FP/GP
24-BIT I/O EXPANDER
ABSOLUTE MAXIMUM RATINGS (Ta = -20 ~ 75C unless otherwise noted)
Symbol VCC VI VO IIK IOK IGND Tstg Supply voltage Input voltage Output voltage Input protection diode current Output parasitic diode current GND current Storage temperature VI<0V VI>VCC VO<0V VO>VCC GND Parameter Conditions Ratings -0.5 ~ +7.0 -0.5 ~ VCC + 0.5 -0.5 ~ VCC + 0.5 -20 20 -20 20 -150 -65 ~ 150 Unit V V V mA mA mA C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Topr Parameter Supply voltage Input voltage Output voltage Operating temperature Min. 2 0 0 -20 Limits Typ. Max. 6 VCC VCC 75 Unit V V V C
ELECTRICAL CHARACTERISTICS (VCC = 2 ~ 6V unless otherwise noted)
Symbol Parameter Test conditions VO=0.1V, VCC-0.1V |IO|=20A VO=0.1V, VCC-0.1V |IO|=20A VO=0.1V, VCC-0.1V |IO|=20A VO=0.1V, VCC-0.1V |IO|=20A VI=VT+, VT- VCC=4.5V VI=VT+, VT- VCC=6V VI=VCC VI=GND VI=VCC, GND Limits Ta=25C Min. Typ. Max. 0.35 0.8 x VCC x VCC 0.2 0.65 x VCC x VCC 0.75 x VCC 0.25 x VCC 0.4 1.0 -1.0 0.1 -0.1 20.0 Ta= -20~75C Min. Max. 0.35 0.8 x VCC x VCC 0.2 0.65 x VCC x VCC 0.75 x VCC 0.25 x VCC 0.5 10.0 -10.0 1.0 -1.0 200.0 Unit
VT+ VT- VIH VIL VOL IO IIH IIL ICC
Upper threshold voltage Lower threshold voltage High-level input voltage Low-level input voltage Open drain low-level output voltage Output leakage current High-level Input leakage current Low-level output leakage current Static power dissipation
V V V V V A A A A
CLK, CS, S, DI
D1 ~ D24
IOL=5mA VO=VCC VO=GND VCC=6.0V VCC=6.0V VCC=6.0V
SWITCHING CHARACTERISTICS (VCC = 5V)
Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Input clock maximum repetitive frequency "L-Z" and "Z-L" outputs propagation time CLK-DO "L-Z" and "Z-L" outputs propagation time CS-D1 to D24 "L-Z" outputs propagation time S=DO, D1 to D24 Test conditions Limits Ta=25C Min. Typ. Max. 2.5 300 300 300 300 300 Ta= -20~75C Min. Max. 1.9 400 400 400 400 400 Unit MHz ns ns ns ns ns
CL=50pF RL=1k (Note)
3
MITSUBISHI DIGITAL ASSP
M66010FP/GP
24-BIT I/O EXPANDER
TIMING CONDITIONS (VCC = 5V)
Limits Symbol tw tsu Parameter CLK, CS and S pulse width DI setup time (in response to CLK) CS setup time (in response to CLK) DI thru D24 setup time (in response to CS) DI hold time (in response to CLK) CS hold time (in response to CLK) D1 thru D24 hold time (in response to CS) CS recovery time (in response to S) Test conditions Ta=25C Min. Typ. Max. 200 100 100 100 100 100 100 100 Ta= -20~75C Min. Max. 260 130 130 130 130 130 130 130 Unit ns ns
th trec
ns ns
NOTE: TEST CIRCUIT
Input
VCC
VCC
RL P.G. 50 GND DUT CL DO, D1~D24
(1) Pulse generator (PG) characteristics: tr=tf=6ns (10% ~ 90%) (2) Capacitance CL includes connection floating capacitance and probe input capacitance.
4
MITSUBISHI DIGITAL ASSP
M66010FP/GP
24-BIT I/O EXPANDER
TIMING CHARTS
tw CLK 50% tPLZ DO 10% 50% tPZL 50% VOL CS tw 50% VCC GND S 50% trec 50% VCC GND VCC GND
tw CS 50% tPLZ D1~D24 10% 50%
tw VCC 50% tPZL 50% VOL 50% GND
tw VCC S 50% tPLZ DO D1~D24 10% VOL 50% GND
DI
50% tsu th 50%
50%
VCC GND VCC GND
CLK
D1~D24
50% tsu th 50%
50%
VCC GND VCC GND
CS
CS
50% tsu th 50% 50%
50%
VCC GND VCC GND
CLK
5

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